Open AccessIris Matching Step Implementation in FPGA
Author(s) -
Aumama M. Farhan,
M. F. Al-Gailani
Publication year - 2019
Publication title -
iraqi journal of information and communication technology/iraqi journal of information and communication technology
Language(s) - English
Resource type - Journals
eISSN - 2789-7362
pISSN - 2222-758X
DOI - 10.31987/ijict.2.1.63
Subject(s) - computer science , field programmable gate array , pipeline (software) , parallel computing , embedded system , generator (circuit theory) , matching (statistics) , computation , identification (biology) , computer hardware , algorithm , operating system , power (physics) , statistics , physics , mathematics , quantum mechanics , botany , biology
Iris recognition system is broadly being utilized as it has distinctive patterns that gives it a powerful strategy to distinguish between persons for identification purposes. However, this system in this implementation requires large memory capacity and high computation time. These factors make us in a challenge to find a way to run this algorithm in a hardware platform. The hardware implementation features reduce the execution time by exploiting the parallelism and pipeline. The present work addresses this issue when reducing execution time by implementing the matching step using hamming distance algorithm on the target device FPGA KINTEX 7 using Xilinx system generator. The obtained result demonstrates that the execution time has been accelerated to 1.32 ns, which is almost at least four times faster than existing works