Open AccessDesign of Low Power Half Adder using Static 125nm CMOS Technology
Author(s) -
G. Hemanth Kumar,
N. Harish,
G. Barath,
D. Ajay,
R. Jagadheeswaran,
G. Naveen Balaji
Publication year - 2018
Publication title -
international journal of engineering and technical research (ijetr)
Language(s) - English
Resource type - Journals
eISSN - 2454-4698
pISSN - 2321-0869
DOI - 10.31873/ijetr.8.9.61
Subject(s) - adder , cmos , power (physics) , electronic engineering , computer science , electrical engineering , engineering , physics , quantum mechanics
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