DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR | Zendy

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DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR

Publication year - 2020

Publication title -

journal of critical reviews

Language(s) - English

Resource type - Journals

ISSN - 2394-5125

DOI - 10.31838/jcr.07.09.212

Subject(s) - branch predictor , parallelism (grammar) , computer science , parallel computing , field programmable gate array , bit (key) , instruction level parallelism , computer architecture , embedded system , arithmetic , mathematics , computer security

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