
CONSTRUCTION OF LOW POWER DIGITAL COMPARATOR IN PSEUDO NMOS LOGIC TO REDUCE THE POWER DISSIPATION
Publication year - 2020
Publication title -
journal of critical reviews
Language(s) - English
Resource type - Journals
ISSN - 2394-5125
DOI - 10.31838/jcr.07.06.345
Subject(s) - nmos logic , comparator , dissipation , power (physics) , electrical engineering , digital electronics , computer science , electronic engineering , engineering , physics , electronic circuit , transistor , voltage , quantum mechanics , thermodynamics