Open AccessElectrical Through Wafer Interconnects with 0.05 Pico Farads Parasitic Capacitance on 400µm Thick Silicon Substrate
Author(s) -
ChingHsiang Cheng,
A.S. Ergun,
B.T. Khuri-Yakub
Publication year - 2002
Publication title -
1998 solid-state, actuators, and microsystems workshop technical digest
Language(s) - English
Resource type - Conference proceedings
DOI - 10.31438/trf.hh2002.40
Subject(s) - wafer , optoelectronics , capacitance , materials science , deep reactive ion etching , parasitic capacitance , substrate (aquarium) , wafer level packaging , silicon , wafer bonding , etching (microfabrication) , wafer scale integration , flip chip , electrical engineering , reactive ion etching , nanotechnology , electrode , engineering , chemistry , layer (electronics) , oceanography , geology , adhesive
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