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A New VLSI Architecture for High-Performance Parallel Turbo Decoder
Author(s) -
Sujatha Elukuru,
SUBHAS CHENNAPALLI,
GIRIPRASAD MAHENDRA NANJAPPA
Publication year - 2022
Publication title -
iium engineering journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.141
H-Index - 6
eISSN - 2289-7860
pISSN - 1511-788X
DOI - 10.31436/iiumej.v23i2.2272
Subject(s) - pipeline (software) , soft decision decoder , computer science , turbo code , turbo equalizer , viterbi decoder , computer hardware , throughput , decoding methods , embedded system , very large scale integration , cmos , computer architecture , parallel computing , wireless , electronic engineering , engineering , algorithm , telecommunications , concatenated error correction code , programming language , block code

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