Open AccessFlip Chip Die-to-Wafer Bonding Review: Gaps to High Volume Manufacturing
Author(s) -
Mario Di Cino,
Feng Li
Publication year - 2022
Publication title -
semiconductor science and information devices
Language(s) - English
Resource type - Journals
ISSN - 2661-3212
DOI - 10.30564/ssid.v4i1.4474
Subject(s) - flip chip , die (integrated circuit) , wafer , wafer bonding , chip , wire bonding , materials science , manufacturing engineering , nanotechnology , engineering , electrical engineering , adhesive , layer (electronics)
Flip chip die-to-wafer bonding faces challenges for industry adoption due to a variety of technical gaps or process integration factors that are not fully developed to high volume manufacturing (HVM) maturity. In this paper,flip-chip and wire bonding are compared, then flip-chip bonding techniques are compared to examine advantages for scaling and speed. Specific recent 3-year trends in flip-chip die-to-wafer bonding are reviewed to address the key gaps and challenges to HVM adoption. Finally, some thoughts on the care needed by the packaging technology for successful HVM introduction are reviewed.