Double Precession Floating Point Multiplier using Schonhage – Strassen Algorithm used for FPGA Accelerator | Zendy

B. Srikanth | Zendy

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Double Precession Floating Point Multiplier using Schonhage – Strassen Algorithm used for FPGA Accelerator

Author(s) -

B. Srikanth

Publication year - 2019

Publication title -

international journal of emerging trends in engineering research

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.218

H-Index - 14

ISSN - 2347-3983

DOI - 10.30534/ijeter/2019/437112019

Subject(s) - field programmable gate array , computer science , floating point , double precision floating point format , multiplication (music) , multiplier (economics) , ieee floating point , strassen algorithm , scalar multiplication , parallel computing , adder , computer hardware , arithmetic , algorithm , mathematics , latency (audio) , matrix multiplication , physics , elliptic curve , quantum mechanics , economics , quantum , mathematical analysis , telecommunications , combinatorics , macroeconomics

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