Open AccessA 40 MHz 70 dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method
Author(s) -
Fernando Paixão Cortes,
Sérgio Bampi
Publication year - 2020
Publication title -
jics. journal of integrated circuits and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.125
H-Index - 11
eISSN - 1872-0234
pISSN - 1807-1953
DOI - 10.29292/jics.v4i1.290
Subject(s) - video graphics array , variable gain amplifier , cmos , automatic gain control , open loop gain , offset (computer science) , electrical engineering , fully differential amplifier , amplifier , operational amplifier , electronic engineering , engineering , computer science , programming language
This paper addresses the design and post-fabrication measurements of a 40 MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70 dB gain control range, using the gm/ID design methodology. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50 mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 μm CMOS process. The VGA dissipates 2.6 mA from a 1.8 V supply, with 34,840 μm2 circuit area, excluding bond-pads.