Open AccessStress Analysis on Ultra Thin Ground Wafers
Author(s) -
Ricardo Cotrin Teixeira,
Koen De Munck,
Piet De Moor,
Kris Baert,
Bart Swinnen,
Chris Van Hoof,
Alexsander Knüettel
Publication year - 2020
Publication title -
jics. journal of integrated circuits and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.125
H-Index - 11
eISSN - 1872-0234
pISSN - 1807-1953
DOI - 10.29292/jics.v3i2.286
Subject(s) - wafer , materials science , stress (linguistics) , grinding , thinning , optoelectronics , interconnection , wafer testing , composite material , computer science , telecommunications , linguistics , philosophy , ecology , biology
Grinding wafers is a well established process for thinning wafers down to 100 μm for use in smart cards and stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in Si wafers thinned down to ~20μm by means of an IR time-of-flight like technique. Such aggressive thinning is a requirement for high density vias interconnect, stacked die packaging and flexible electronics. We found that the thinning process used did not add significant stress value on the thinned wafer.