Open AccessCore Communication Interface for FPGAs
Author(s) -
J.C.S. Palma,
Ana Maria Lisboa de Mello,
Leandro Möller,
Fernando Moraes,
Ney Calazans
Publication year - 2020
Publication title -
jics. journal of integrated circuits and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.125
H-Index - 11
eISSN - 1872-0234
pISSN - 1807-1953
DOI - 10.29292/jics.v1i1.254
Subject(s) - field programmable gate array , interface (matter) , computer science , embedded system , interconnection , core (optical fiber) , computer architecture , computer hardware , computer network , operating system , telecommunications , bubble , maximum bubble pressure method
The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic interconnection of hard IP cores. The approach targets system-on-a-chip designs build in a single FPGA device. The paper proposes a communication interface that allows IP cores replacement during the FPGA normal operation. The same interface also allows the communication among distinct IP cores to take place.