Open AccessExploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures
Author(s) -
Andre N. Sapper,
Guilherme Paim,
Eduardo Costa,
Sérgio Bampi
Publication year - 2021
Publication title -
jics. journal of integrated circuits and systems
Language(s) - English
Resource type - Journals
eISSN - 1872-0234
pISSN - 1807-1953
DOI - 10.29292/jics.v16i2.226
Subject(s) - cordic , fast fourier transform , computer science , split radix fft algorithm , parallel computing , clock gating , prime factor fft algorithm , computer hardware , power (physics) , digital signal processing , power of two , clock rate , algorithm , fourier transform , clock signal , clock skew , field programmable gate array , mathematics , fourier analysis , mathematical analysis , telecommunications , physics , jitter , short time fourier transform , quantum mechanics , chip
This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.