Open AccessDigital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
Author(s) -
Egon Henrique Salerno Galembeck,
Denis Flandre,
Christian Renaux,
Salvador Pinillos Gimenez
Publication year - 2019
Publication title -
jics. journal of integrated circuits and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.125
H-Index - 11
eISSN - 1872-0234
pISSN - 1807-1953
DOI - 10.29292/jics.v14i2.34
Subject(s) - silicon on insulator , mosfet , materials science , optoelectronics , transistor , cmos , planar , electrical engineering , electronic engineering , silicon , computer science , engineering , voltage , computer graphics (images)
This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.