Open AccessVERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH
Author(s) -
Anuradha M. Sandi
Publication year - 2020
Publication title -
international journal of engineering technologies and management research
Language(s) - English
Resource type - Journals
ISSN - 2454-1907
DOI - 10.29121/ijetmr.v6.i6.2019.392
Subject(s) - adder , carry (investment) , serial binary adder , carry save adder , computer science , look ahead , arithmetic , computer hardware , very large scale integration , electronic circuit , mathematics , algorithm , electrical engineering , engineering , embedded system , telecommunications , finance , economics , latency (audio)
In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.