Open AccessSURVEY ON DISTRIBUTED CANNY EDGE DETECTOR WITH FPGA
Author(s) -
Poonam S. Deokar,
Anagha P. Khedkar
Publication year - 2015
Publication title -
international journal of research - granthaalayah
Language(s) - English
Resource type - Journals
eISSN - 2394-3629
pISSN - 2350-0530
DOI - 10.29121/granthaalayah.v3.i3.2015.3031
Subject(s) - canny edge detector , deriche edge detector , computer science , image gradient , edge detection , field programmable gate array , pixel , artificial intelligence , enhanced data rates for gsm evolution , block (permutation group theory) , computer vision , detector , image processing , algorithm , image (mathematics) , mathematics , computer hardware , telecommunications , geometry
The Edge can be defined as discontinuities in image intensity from one pixel to another. Modem image processing applications demonstrate an increasing demand for computational power and memories space. Typically, edge detection algorithms are implemented using software. With advances in Very Large Scale Integration (VLSI) technology, their hardware implementation has become an attractive alternative, especially for real-time applications. The Canny algorithm computes the higher and lower thresholds for edge detection based on the entire image statistics, which prevents the processing of blocks independent of each other. Direct implementation of the canny algorithm has high latency and cannot be employed in real-time applications. To overcome these, an adaptive threshold selection algorithm may be used, which computes the high and low threshold for each block based on the type of block and the local distribution of pixel gradients in the block. Distributed Canny Edge Detection using FPGA reduces the latency significantly; also this allows the canny edge detector to be pipelined very easily. The canny edge detection technique is discussed in this paper.