Open AccessImproving Robustness of Dual Port SRAM by finding additional bugs in design using ESPCV flow to compare Schematics v/s Verilog on 12LP GF Technology as an example
Author(s) -
Sneha Sharma,
Madhu Shandilya,
O.P. Meena,
Naresh Gandham
Publication year - 2019
Publication title -
international journal of innovative research in applied sciences and engineering
Language(s) - English
Resource type - Journals
ISSN - 2456-8910
DOI - 10.29027/ijirase.v3.i11.2019.423-427
Subject(s) - schematic , verilog , robustness (evolution) , computer science , computer architecture , static random access memory , embedded system , mathematics , computer hardware , electronic engineering , engineering , field programmable gate array , chemistry , biochemistry , gene