Open AccessFAILURE TOLERANT SYNCHRONOUS AND SELT-TIED CIRCUITS COMPARISON
Author(s) -
A. A. Zatsarinny,
Yury Stepchenkov,
Yuri Diachenko,
Yuri Rogdestvenski
Publication year - 2021
Language(s) - English
Resource type - Conference proceedings
DOI - 10.29003/m2498.mmmsec-2021/154-156
Subject(s) - computer science , electronic circuit , modular design , fault tolerance , coding (social sciences) , error detection and correction , digital electronics , embedded system , distributed computing , electrical engineering , algorithm , engineering , statistics , mathematics , operating system
The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance