Open AccessSUPPLY NOISE REDUCTION VERIFICATION IN PRE-LAYOUT AND POST-LAYOUT STAGES FOR SYSTEM-ON-CHIP
Author(s) -
Partha P. Mitra
Publication year - 2020
Publication title -
journal of mechanics of continua and mathematical sciences
Language(s) - English
Resource type - Journals
eISSN - 2454-7190
pISSN - 0973-8975
DOI - 10.26782/jmcms.2020.07.00016
Subject(s) - chip , reduction (mathematics) , computer science , noise (video) , noise reduction , integrated circuit layout , ic layout editor , embedded system , electronic engineering , computer hardware , engineering , electrical engineering , integrated circuit , circuit extraction , telecommunications , mathematics , artificial intelligence , voltage , operating system , geometry , image (mathematics) , equivalent circuit