Open AccessA 4-μW 0.8-V Rail-to-Rail Input/Output CMOS Fully Differential OpAmp
Author(s) -
M. R. Valero,
S. Celma,
N. Medrano
Publication year - 1970
Publication title -
jornada de jóvenes investigadores del i3a
Language(s) - English
Resource type - Journals
ISSN - 2341-4790
DOI - 10.26754/jji-i3a.201201801
Subject(s) - operational amplifier , phase margin , slew rate , cmos , input offset voltage , electrical engineering , operational transconductance amplifier , amplifier , engineering , frequency compensation , open loop gain , control theory (sociology) , voltage , electronic engineering , computer science , control (management) , artificial intelligence
This paper presents an ultra low power rail-to-rail input/output operational amplifier (OpAmp) designed in a low cost 0.18 μm CMOS technology. In this OpAmp, rail-to-rail input operation is enabled by using complementary input pairs with gm control. To maximize the output swing a rail-to-rail output stage is employed. For low-voltage low-power operation, the operating transistors in the input and output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, and the slew-rate is 0.04 V/μs with a 10 pF capacitive load connected to each of the amplifier outputs. For the same load, the simulated unity gain frequency is 131 kHz with a 64º phase margin. A common-mode feed-forward circuit (CMFF) increases CMRR, reducing drastically the variations in the output common mode voltage and keeping the DC gain almost constant. In fact, their relative error remains below 1.2 % for a (-20ºC, +120ºC) temperature span. In addition, the proposed OpAmp is very simple and consumes only 4 μW at 0.8 V supply.