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A SINGLE BIT ERROR DETECTION AND CORRECTION BASED ON THEMRC AND THE MP TECHNIQUES IN RRNS ARCHITECTURE
Author(s) -
Yaw Afriyie
Publication year - 2018
Publication title -
international journal of advanced research in computer science
Language(s) - English
Resource type - Journals
ISSN - 0976-5697
DOI - 10.26483/ijarcs.v9i3.6113
Subject(s) - computer science , adder , error detection and correction , architecture , computer hardware , scheme (mathematics) , speedup , residue number system , algorithm , parallel computing , computer engineering , latency (audio) , mathematics , telecommunications , art , mathematical analysis , visual arts

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