Open AccessCOMPARISON OF INSTRUCTION SCHEDULING AND REGISTER ALLOCATION FOR MIPS AND HPL-PD ARCHITECTURE FOR EXPLOITATION OF INSTRUCTION LEVEL PARALLELISM
Author(s) -
Rajendra Kumar
Publication year - 2018
Publication title -
engineering heritage journal
Language(s) - English
Resource type - Journals
eISSN - 2521-0904
pISSN - 2521-0440
DOI - 10.26480/gwk.01.2018.04.08
Subject(s) - register allocation , computer science , parallel computing , instruction level parallelism , processor register , instruction scheduling , scheduling (production processes) , computer architecture , architecture , register file , parallelism (grammar) , instruction set , operating system , dynamic priority scheduling , rate monotonic scheduling , operations management , engineering , schedule , art , semiconductor memory , compiler , visual arts , memory address
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