Open AccessImprovement in the LDPC Error Correction Process Based on FPGA Implementation
Author(s) -
Tarigan Aditia,
Rita Purnamasari,
Efa Maydhona Saputra
Publication year - 2015
Publication title -
jmecs (journal of measurements, electronics, communications, and systems)
Language(s) - English
Resource type - Journals
ISSN - 2477-7986
DOI - 10.25124/jmecs.v1i1.1476
Subject(s) - low density parity check code , computer science , error detection and correction , message passing , field programmable gate array , forward error correction , matrix (chemical analysis) , algorithm , coding (social sciences) , process (computing) , decoding methods , parallel computing , computer hardware , mathematics , statistics , materials science , composite material , operating system
LDPC is one of channel coding technique which can achieve the nearest to the shannon limit. The focus of this paper is to give improvement for LDPC error correcting process using message passing algorithm. This works used FPGA Cyclon II for implementing the process. This paper worked with two different LDPC matrix, matrix (8, 16) and matrix (24, 48). Matrix (24,48) had wc = 4 and wr = 8. Matrix (8, 16) had wc = 2 and wr = 4. The comparison of these two matrix would present the effects in the error correcting decision for message passing algorithm and the effect for implementing the algorithm on FPGA Cyclon II. This research purpose was to prove message passing algorithm can provide more than one bit error correction.