Open AccessThermal distribution and reliability prediction for 3D Networks-on-Chip
Author(s) -
Khanh N. Dang,
Akram Ben Ahmed,
Abderazek Ben Abdallah,
XuanTu Tran
Publication year - 2020
Publication title -
tạp chí khoa học đại học quốc gia hà nội: công nghệ thông tin - truyền thông (vnu journal of science: computer science and communication engineering)
Language(s) - English
Resource type - Journals
eISSN - 2615-9260
pISSN - 2588-1086
DOI - 10.25073/2588-1086/vnucsce.245
Subject(s) - three dimensional integrated circuit , bandwidth throttling , reliability (semiconductor) , computer science , junction temperature , chip , network on a chip , transient (computer programming) , mpsoc , design flow , mean time between failures , thermal , reliability engineering , power (physics) , electronic engineering , embedded system , system on a chip , engineering , failure rate , mechanical engineering , telecommunications , physics , quantum mechanics , meteorology , gas compressor , operating system
As one of the most promising technologies to reduce footprint, power consumption and wire latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for VLSI system. Combining with the Network-on-Chip infrastructure to obtain 3D Networks-on-Chip (3D-NoCs), the new on-chip communication paradigm brings several advantages. However, thermal dissipation is one of the most critical challenges for 3D-ICs, where the heat cannot easily transfer through several layers of silicon. Consequently, the high-temperature area also confronts the reliability threat as the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s model. Apparently, 3D-NoCs and 3D ICs must tackle this fundamental problem in order to be widely used. However, the thermal analyses usually require complicated simulation and might cost an enormous execution time. As a closed-loop design flow, designers may take several times to optimize their designs which significantly increase the thermal analyzing time. Furthermore, reliability prediction also requires both completed design and thermal prediction, and designer can use the result as a feedback for their optimization. As we can observe two big gaps in the design flow, it is difficult to obtain both of them which put 3D-NoCs under thermal throttling and reliability threats. Therefore, in this work, we investigate the thermal distribution and reliability prediction of 3D-NoCs. We first present a new method to help simulate the temperature (both steady and transient) using traffic values from realistic and synthetic benchmarks and the power consumption from standard VLSI design flow. Then, based on the proposed method, we further predict the relative reliability between different parts of the network. Experimental results show that the method has an extremely fast execution time in comparison to the acceleration lifetime test. Furthermore, we compare the thermal behavior and reliability between Monolithic design and TSV-based design. We also explore the ability to implement the thermal via a mechanism to help reduce the operating temperature.