Open AccessLow Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing
Author(s) -
Shilpa Sathish,
C. Lakshminarayana
Publication year - 2012
Publication title -
international journal of computer and technology
Language(s) - English
Resource type - Journals
ISSN - 2277-3061
DOI - 10.24297/ijct.v2i3b.2699
Subject(s) - very large scale integration , computer science , parallel computing , power (physics) , software pipelining , computer architecture , reduction (mathematics) , parallel processing , embedded system , software , mathematics , physics , geometry , quantum mechanics , programming language
The main objectives of any VLSI design are Power, Delay andArea. Minimizing all the objectives is a challenge in presentsituation but all efforts to achieve one of these can lead to abetter design. This paper proposes an EDA tool for low power/high speed VLSI design, which solves any DFG to estimate thespeed of operation and the percentage reduction in the powerconsumption using pipelining and parallel processing concepts