Open AccessHYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS
Author(s) -
Belgacem Hamdi,
Khaled Ben Khalifa,
Aymen Fradi
Publication year - 2013
Publication title -
international journal of computer and technology
Language(s) - English
Resource type - Journals
ISSN - 2277-3061
DOI - 10.24297/ijct.v10i6.7025
Subject(s) - adder , cmos , computer science , logic gate , overhead (engineering) , carry (investment) , pass transistor logic , electronic engineering , transistor , computer hardware , algorithm , engineering , electrical engineering , finance , voltage , economics , operating system
In this paper we present an efficient design for self-checking fast adders data paths. We investigate the implementation of concurrent error detection fast adders: carry look-ahead, Carry skip, Carry-select and Conditional-Sum adders. To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). They are fully differential and checked by dual-rail and parity codes.