Open AccessA New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer
Author(s) -
Hussein Shakor Moghee
Publication year - 2018
Publication title -
mağallaẗ diyālá li-l-ʿulūm al-handasiyyaẗ/mağallaẗ diyālá li-l-ʻulūm al-handasiyyaẗ
Language(s) - English
Resource type - Journals
eISSN - 2616-6909
pISSN - 1999-8716
DOI - 10.24237/djes.2018.11208
Subject(s) - modelsim , verilog , computer science , application specific integrated circuit , embedded system , state (computer science) , field programmable gate array , finite state machine , power (physics) , hardware description language , adder , power consumption , logic synthesis , computer hardware , computer architecture , logic gate , vhdl , programming language , algorithm , telecommunications , physics , quantum mechanics , latency (audio)
This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU using tri-state logic which is not necessary to use, except the required processes. In this work, the suggested design is realized by using ASIC methodologies. In order to implement the arithmetic and logic architectures, 130 nm standard cell libraries are used for ASIC execution. The architecture of the design has been created using Verilog HDL language. In addition, it is simulated using ModelSim-Altera 10.3c (Quartus II 14.1) tools. By using tri-state technique, dynamic power and total power are decreased