z-logo
open-access-imgOpen Access
Low Power and High Speed DFT Architecture
Author(s) -
Ahmed K. Jameil
Publication year - 2016
Publication title -
diyala journal of engineering sciences
Language(s) - English
Resource type - Journals
eISSN - 2616-6909
pISSN - 1999-8716
DOI - 10.24237/djes.2016.09408
Subject(s) - field programmable gate array , adder , computer science , architecture , discrete fourier transform (general) , computation , power (physics) , power consumption , fast fourier transform , embedded system , computer hardware , computer architecture , fourier transform , algorithm , telecommunications , mathematics , fractional fourier transform , art , fourier analysis , mathematical analysis , physics , quantum mechanics , visual arts , latency (audio)

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here
Accelerating Research

Address

John Eccles House
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom