
An Efficient Parallel Algorithm for Latin Square Design: A Multi Core CPU Approach
Author(s) -
Abhay B. Rathod,
Sanjay M. Gulhane
Publication year - 2017
Publication title -
international journal of system modeling and simulation
Language(s) - English
Resource type - Journals
ISSN - 2518-0959
DOI - 10.24178/ijsms.2017.2.2.27
Subject(s) - speedup , latin square , computer science , parallel computing , algorithm , parallel algorithm , square (algebra) , mathematics , rumen , chemistry , geometry , food science , fermentation
— The theory of Latin squares is very important tool in design theory. Like much of design theory, Latin squares have various applications in statistics, finite geometries and experimental design, to name a few. In this paper, we proposed an efficient parallel algorithm for Latin square design which have desirable properties for parallel array access. These squares provide conflict free access to various subsets of an n x n array using n memory modules. A transversal of such a square is a set of n entries such that no two entries share the same row, column or symbol. We present a general construction method for building parallel Latin square of order n2 for all n.
The proposed algorithm presents a quick parallel method to produce a Latin square design and a parallel conflict access of data in SIMD system. The simulation results of the proposed parallel algorithm for Latin square design were compared with the traditional sequential algorithm Latin square design in terms of speedup and efficiency. The results of parallel Latin Square design were very promising and showed a potential that this design could successfully be applied to the parallel routing problems for conflict free data access. At last, the results show that the parallel versions of former sequential algorithm with simple modifications achieve the super linear speedup up to 200 times for matrix size of 256.
Index Terms: Latin square, multi core processor, parallel processing, simulation, parallel memory system, skewing scheme, multistage interconnection network.