Open AccessA latency optimized biased implementation style weak-indication self-timed full adder
Author(s) -
P. Balasubramanian
Publication year - 2015
Publication title -
facta universitatis. series electronics and energetics/facta universitatis. series: electronics and energetics
Language(s) - Uncategorized
Resource type - Journals
eISSN - 2217-5997
pISSN - 0353-3670
DOI - 10.2298/fuee1504657b
Subject(s) - adder , serial binary adder , carry save adder , computer science , latency (audio) , cmos , computer hardware , electronic engineering , arithmetic , parallel computing , mathematics , engineering , telecommunications