Open AccessLayout considerations for high temperature SRAM cells in a SOI technology
Author(s) -
Sonja Richter,
Stefan Bormann,
V. Nakov
Publication year - 2003
Publication title -
facta universitatis. series electronics and energetics/facta universitatis. series: electronics and energetics
Language(s) - English
Resource type - Journals
eISSN - 2217-5997
pISSN - 0353-3670
DOI - 10.2298/fuee0302205r
Subject(s) - silicon on insulator , static random access memory , leakage (economics) , cmos , electronic engineering , electrical engineering , engineering , computer science , materials science , silicon , optoelectronics , economics , macroeconomics
Silicon-on-insulator technologies are well suited for high temperature circuit design, due to low leakage currents. The reduction of leakage currents is especially important in large repetitive structures such as memories. This paper describes the layout development of a high temperature SRAM cell in a SOI Technology. First, the differences between SOI technologies and standard CMOS processes are presented. It is then discussed, how SOI specific circuit element behavior affects the layout design of different parts of the SRAM cell. Solutions for SOI specific problems are presented and advantages and disadvantages of SOI technologies in static random access memory design are shown.