Open AccessFPGA implementation of folded FIR filter architecture with changeable folding factor
Author(s) -
Ivan Milentijević,
Vladimir Ćirić,
T.I. Tokic,
Oliver Vojinović
Publication year - 2002
Publication title -
facta universitatis. series electronics and energetics/facta universitatis. series: electronics and energetics
Language(s) - English
Resource type - Journals
eISSN - 2217-5997
pISSN - 0353-3670
DOI - 10.2298/fuee0203451m
Subject(s) - folding (dsp implementation) , field programmable gate array , computer science , vhdl , filter (signal processing) , throughput , finite impulse response , signal flow graph , parallel computing , transformation (genetics) , computer hardware , computational science , computer architecture , algorithm , engineering , computer vision , telecommunications , biochemistry , chemistry , electrical engineering , wireless , gene
The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor on to the fixed size array is described in this paper. The bit-level transformation of the original data flow graph (DFG), for the bit-plane architecture, that provides the successful application of the folding technique with changeable folding is presented at transfer function level The mathematical path that describes the transformation is given, and implications at the DFG level are discussed. Changeable folding sets are involved with aim to increase the throughput of the folded system reducing the folding factor according to the coefficient length. The folded FIR filter architecture is described in VHDL as a parameterized FIR filtering core and implemented in FPGA technology. The design "tradeoffs" relating on the occupation of the chip resources and achieved throughputs are presented.