Open AccessHIGH SPEED AND AREA-EFFECTIVE VLSI ARCHITECTURE OF THREE- OPERAND ADDER USING TANNER EDA TOO
Author(s) -
S. A. Sivakumar,
JUTURU LAKSHMI,
R. Keerthana,
K P Bharath
Publication year - 2021
Publication title -
international journal of advanced trends in engineering science and technology
Language(s) - English
Resource type - Journals
ISSN - 2456-1126
DOI - 10.22413/ijatest/2021/v6/i3/4
Subject(s) - operand , adder , very large scale integration , parallel computing , computer science , arithmetic , speedup , architecture , computer architecture , mathematics , embedded system , telecommunications , latency (audio) , geography , archaeology
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