Open AccessA Non Linear PUF Circuit Design for Two Factor Authentication in IoT Cryptography
Author(s) -
Krishna Priya Gurumanapalli,
Nagendra Muthuluru
Publication year - 2021
Publication title -
international journal of intelligent engineering and systems
Language(s) - English
Resource type - Journals
eISSN - 2185-310X
pISSN - 1882-708X
DOI - 10.22266/ijies2021.0228.17
Subject(s) - computer science , authentication (law) , field programmable gate array , physical unclonable function , cryptography , embedded system , internet of things , spartan , mutual authentication , computer hardware , block (permutation group theory) , computer network , computer security , geometry , mathematics
Internet-of-Things (IoT) is growing network paradigm which enables mutual communication between the user and smart devices using the internet. The IoT devices are susceptible to the security threats, due to placement of restricted computational capabilities of the computing devices in IoT. The conventional encryption algorithm utilizes the high amount of resource block in it which increases the area and power. Moreover, Two Factor Authentication (TFA) scheme based authentication protocols does not have the efficiency to secure the data. Because the random number generated by the TFA is ideal for all IoT devices which are easy to hack by the unauthorized persons. In this Research paper, the Linear Feedback Shift Register (LFSR) based Reconfigurable Physical Unclonable Function (RPUF) is proposed to overcome the security issues caused in the IoT communication. The RPUF is designed based on the LFSR to generate the random number for every clock cycle. Normally, reconfigurable process helps to generate the different output values for every clock cycle. But, it failed to generate different outputs for same input values. Here, LFSR based RPUF helps to generated the different response values even the same challenge is given to the input side. The Lightweight TFA scheme is presented for IoT, where PUF has been considered as one of the major authentication factors. At last, Spartan 6 and Virtex 6 Field Programmable Gate Array (FPGA) performances are calculated for proposed TFA-RPUF-IoT and existing TFA-PUF-IoT protocols. In Spartan 6, TFA-RPUF-IoT protocol occupied 11 slices, 31 LUTs, 42 flip flops which are less compared to conventional TFA-PUF-IoT.