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VLSI Architecture of Encoding using Sols Technique for Reducing Power in DSRC
Author(s) -
N Kokila,
M. Tech,
B Malleshwari
Publication year - 2017
Publication title -
international journal of emerging engineering research and technology
Language(s) - English
Resource type - Journals
eISSN - 2349-4409
pISSN - 2349-4395
DOI - 10.22259/ijeert.0501002
Subject(s) - dedicated short range communications , very large scale integration , encoding (memory) , architecture , computer science , computer architecture , power (physics) , embedded system , telecommunications , geography , wireless , artificial intelligence , physics , archaeology , quantum mechanics

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