Open AccessHardware Realization of Low Power and Area Efficient Vedic Mac in DSP Filters
Author(s) -
Ms. D. Ramadevi,
Kota Pavan Kalyan,
B. S. ANIL,
P. Sirisha,
N. Pallavi,
M. Pratyush
Publication year - 2022
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2022.45208
Subject(s) - adder , computer science , realization (probability) , carry save adder , carry (investment) , arithmetic , computer hardware , key (lock) , power (physics) , digital signal processing , very large scale integration , filter (signal processing) , process (computing) , multiplication (music) , finite impulse response , embedded system , mathematics , telecommunications , algorithm , statistics , physics , operating system , computer security , finance , quantum mechanics , combinatorics , economics , computer vision , latency (audio)