Open AccessDesign of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review
Author(s) -
C Rohan
Publication year - 2022
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2022.44654
Subject(s) - computer science , pipeline (software) , reduced instruction set computing , embedded system , interrupt , instructions per cycle , instruction set , universal asynchronous receiver/transmitter , control unit , computer hardware , benchmark (surveying) , pipeline burst cache , cache , cpu cache , parallel computing , operating system , central processing unit , chip , cache algorithms , telecommunications , microcontroller , geodesy , geography