Open AccessA Review on Design and Analysis of Low Power PLL for Digital Applications and Multiple Clocking Circuits
Author(s) -
Pooja Thool,
J. D Dhande,
Prof. Y. A. Sadawarte
Publication year - 2022
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2022.41193
Subject(s) - phase locked loop , cmos , pll multibit , electronic engineering , computer science , power (physics) , digital electronics , electronic circuit , electrical engineering , engineering , jitter , physics , quantum mechanics
A phase locked loop (PLL) is a basic element of many communication and instrumentation domain. This paper discusses the challenges in designing the low power PLL for multiple frequency output for digital applications. PLL is a key element providing clocking scheme in many electronic circuits raises the requirement of decreasing the power, with the advancement in CMOS technology. In this work, we provide review on low power PLL with good stability. Keywords: Phase-locked loop, CMOS, Clocking, low Power, Digital Applications, etc.