Open AccessDesign and Implementation of Floating-Point Addition and Floating-Point Multiplication
Author(s) -
Nagireddy Kavya
Publication year - 2022
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2022.39742
Subject(s) - floating point , multiplication (music) , adder , verilog , computer science , double precision floating point format , point (geometry) , reduction (mathematics) , single precision floating point format , ieee floating point , arithmetic , floating point unit , multiplication algorithm , computer hardware , field programmable gate array , algorithm , mathematics , binary number , telecommunications , geometry , combinatorics , latency (audio)
In this paper, we present the design and implementation of Floating point addition and Floating point Multiplication. There are many multipliers in existence in which Floating point Multiplication and Floating point addition offers a high precision and more accuracy for the data representation of the image. This project is designed and simulated on Xilinx ISE 14.7 version software using verilog. Simulation results show area reduction and delay reduction as compared to the conventional method. Keywords: FIR Filter, Floating point Addition, Floating point Multiplication, Carry Look Ahead Adder