Open AccessSimulation and Analysis of different CMOS Full Adders for Delay Optimisation
Author(s) -
Nakul C. Kubsad
Publication year - 2021
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2021.37924
Subject(s) - adder , transmission gate , computer science , cmos , nmos logic , electronic engineering , transistor , cadence , serial binary adder , carry save adder , power–delay product , propagation delay , electrical engineering , computer hardware , voltage , engineering
Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.