Open AccessVerification of Wishbone Bus Interface for SoC using System Verilog and UVM
Author(s) -
Pooja. D. R
Publication year - 2021
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2021.36282
Subject(s) - verilog , computer science , embedded system , functional verification , interface (matter) , system on a chip , computer architecture , computer hardware , formal verification , field programmable gate array , operating system , programming language , bubble , maximum bubble pressure method
The Verification phase carries important role in design cycle of a system on chip. Verification gives with the actual enactment and functionality of a DUT and to verify the design meets the system requirements. This paper present wishbone bus interface for soc integration to interconnect architecture for portable IP cores and test bench is developed in system Verilog and verification is done by both system Verilog verification methodology and universal verification methodology which includes scoreboard, functional coverage and assertion. This paper based on two application to integrate IP cores that is single master with single slave interconnection and single master with multiple slave interconnections where master is test bench and slave will be a core.