Open AccessVerification of Open Core Protocol using System Verilog and UVM
Author(s) -
. Darshan
Publication year - 2021
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2021.36213
Subject(s) - verilog , computer science , functional verification , dataflow , intelligent verification , protocol (science) , verification , runtime verification , high level verification , very large scale integration , embedded system , software verification , formal verification , computer architecture , programming language , field programmable gate array , software , software system , medicine , software construction , alternative medicine , pathology
The ever-increasing complexity of the integrated circuits design and the scale of the projects are making verification more challenging and time-consuming. As a result, the rapidly expanding VLSI industry necessitates a highly reliable and robust verification mechanism. In this paper, System Verilog Verification and Universal Verification Methodologies were adopted to verify the Accellera Open Core Protocol 3.0 as per specifications. According to the verification plan, the environment was developed under a dynamic approach, and the passive aspects included scoreboard, functional coverage, and system verilog assertions. The presented frameworks had verified OCP achieving successful dataflow signals extensions as per results.