Open AccessLow Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Author(s) -
Madabhushi Sai Meghana
Publication year - 2021
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2021.35286
Subject(s) - xnor gate , schematic , adder , power–delay product , computer science , logic gate , electronic engineering , power (physics) , serial binary adder , cmos , computer hardware , engineering , nand gate , physics , quantum mechanics
In this project, novel circuits for FULL ADDER are proposed using new XOR or XNOR gates. The conventional design of XOR or XNOR gates shows that the not gate in the schematic has drawbacks. So by investigating advanced XOR or XNOR gates we proposed the schematic design. The proposed schematics are optimized in terms of speed, delay, power and power delay product. We developed six novel hybrid full adder schematics based on exploring new XOR or XNOR gates. Each designed schematics have their specifications of energy consumption, delay, power delay product. To simulate the performance of the proposed designs, we use mentor graphics, tanner tool. The simulation yields a 45-nm CMOS innovation model that focuses on the proposed plans having best speed and power other than the plan of any full adder. The proposed Full Adders has 2-28% increment in consumption of energy and power delay product compared to other design schematics. The proposed hybrid full adders are investigated with voltage 1.8V, speed ,size of transistors, area, power consumption and delay.