Open AccessA Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics
Author(s) -
Rajesh Deokate
Publication year - 2021
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2021.35242
Subject(s) - multiplier (economics) , vhdl , arithmetic , multiplication (music) , computer science , floating point , digital signal processing , ieee floating point , binary number , single precision floating point format , complex multiplication , mathematics , computer hardware , field programmable gate array , algorithm , elliptic curve , mathematical analysis , combinatorics , economics , macroeconomics
The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.