Open AccessDesign and Implementation of a 32-bit Floating Point Unit
Author(s) -
Kishan Maladkar
Publication year - 2021
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2021.35052
Subject(s) - floating point unit , floating point , computer science , verilog , multiplier (economics) , digital signal processing , single precision floating point format , computer hardware , arithmetic , arithmetic logic unit , subtraction , ieee floating point , double precision floating point format , booth's multiplication algorithm , multiplication (music) , digital signal processor , adder , division (mathematics) , 32 bit , field programmable gate array , mathematics , algorithm , telecommunications , combinatorics , economics , macroeconomics , latency (audio)
A Floating Point Unit is a math co-processor that is in the most demand of Digital Signal Processing (DSP), Processors and more. It is used to perform functions or operations on floating point numbers like addition, subtraction, multiplication, division, square root and more. It is specifically designed to carry out mathematical operations and it can be emulated in CPU. Floating point unit is a common operation used in advanced Digital Signal Processing and various processor applications. The aim was to develop an optimized floating point unit so that the delay was reduced and efficiency was increased. The floating point unit has been written according to IEEE 754 standard and the entire design has been coded in Verilog HDL. The results are improved by 12% with the usage of Vedic multiplier that is a delay of 4.450ns as compared to 5.123ns with an array multiplier. Designs can be further optimized using low power designing techniques at architectural level. Different behaviour can be observed for different size and technologies.