
Implementation of 4x4 Data bit Multiplier using Dadda Algorithm and Optimized Full Adder
Author(s) -
Siddhardha Sathanapally
Publication year - 2020
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2020.5151
Subject(s) - adder , computer science , multiplier (economics) , algorithm , arithmetic , bit (key) , parallel computing , 16 bit , computer hardware , mathematics , telecommunications , computer network , latency (audio) , macroeconomics , economics