Open AccessDesign and Testing Parallel Prefix Adders using Reconfigurable LFSR in FPGA
Author(s) -
Soujanya Munnur
Publication year - 2019
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2019.4630
Subject(s) - adder , field programmable gate array , parallel computing , arithmetic , computer science , prefix , linear feedback shift register , embedded system , shift register , mathematics , telecommunications , linguistics , philosophy , chip , latency (audio)
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