
Design and Performance Comparison of 16-Bit UT Multiplier using Reversible Logic
Author(s) -
K. Yogeswari
Publication year - 2019
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2019.4161
Subject(s) - multiplier (economics) , arithmetic , computer science , bit (key) , mathematics , algorithm , computer network , economics , keynesian economics