
Design of the 16-bit Vedic Multiplier Based on Compressor Adder
Author(s) -
Harshit Swaroop
Publication year - 2018
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2018.1472
Subject(s) - adder , arithmetic , multiplier (economics) , gas compressor , bit (key) , computer science , mathematics , engineering , telecommunications , computer security , economics , mechanical engineering , keynesian economics , latency (audio)