Open AccessDesign and Operational Synthesis of 64-bit Adder and Subtracter Unit using Delay Efficient Parallel Prefix Technique
Author(s) -
Akash Tiwari
Publication year - 2018
Publication title -
international journal for research in applied science and engineering technology
Language(s) - English
Resource type - Journals
ISSN - 2321-9653
DOI - 10.22214/ijraset.2018.1442
Subject(s) - adder , arithmetic , prefix , computer science , bit (key) , carry save adder , unit (ring theory) , computer hardware , parallel computing , mathematics , telecommunications , computer network , linguistics , philosophy , mathematics education , latency (audio)