Open AccessDevelopment of memory controller for today’s Elbrus microprocessors
Author(s) -
Игорь Петров
Publication year - 2019
Publication title -
radiopromyšlennostʹ
Language(s) - English
Resource type - Journals
eISSN - 2541-870X
pISSN - 2413-9599
DOI - 10.21778/2413-9599-2019-29-3-41-47
Subject(s) - microprocessor , computer science , chip , reliability (semiconductor) , embedded system , controller (irrigation) , bandwidth (computing) , energy consumption , engineering , electrical engineering , telecommunications , power (physics) , physics , quantum mechanics , agronomy , biology
The introduction of a new generation of microprocessors that belong to the Elbrus family and involve the introduction of a network-on-chip, requires the development of efficient means of access to DDR random access memory channels for network nodes. The paper includes a solution to this issue related to the interaction between DDR4 RAM and Elbrus-16СВ, 16-core microprocessor, which demands higher standards of an available capacity and peak bandwidth of memory channels. When designing Elbrus-16CB microprocessor, higher energy efficiency and reliability are also between main objectives. When performing the tasks set, an important component was adaptation of the memory controller, successfully applied in the microprocessors produced by MCST JSC, to DDR4 3DS standard compliance, taken as a basis for the use in a number of recent developments. It provides a four-time higher available RAM capacity without a directly proportional growth of energy consumption. The paper includes a structure of the memory controller and made decisions. These make it possible to increase the target frequency in operations of the device by 30% up to 800 MHz and increase operation reliability of the memory channel.